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Fab10 QEM PQE C1+ Yield Engineering Engineer/Senior Engineer

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Date: Jun 26, 2019

Location: Singapore, 03, SG

Company: Micron


Req. ID: 133462 

As a QEM PQE Engineer at Micron Technology, Inc., you will support the semiconductor memory manufacturing efforts for developing, validating, characterizing, and qualifying new non-volatile memory products, enabling volume manufacturing with improved frontend C1/C1+ test yields as well as backend OPS/PTS/Cum Yield performance and enhance overall reliability by supporting the team in doing yield and failure analysis to identify root cause fail signatures and other C1/C1+ yield limiters. You will be responsible for the development of memory-test patterns, analyzing electrical failures, improvement of yield as well as overall cell performance, debug, design, simulation and implementation of circuit and process changes on test chips.  You will leverage an understanding of electrical operation and current fabrication technology of advanced DRAM/NAND memory products. You will be expected to do high level bench electrical characterization and how physical defects and process problems relate to electrical signatures. You will be expected to interact with engineers and technicians across multiple sites responsible for corrective actions (Design, Product Engineering, Research & Development, Test, Quality and Reliability Assurance).


  • Responsible for new product startup and yield improvement
  • Support design verification and in-depth circuit of new products using CAD tools and Verilog simulations
  • Work with the wafer fab process/integration group to address process-related defects affecting product yield
  • Perform bench validation to support product characterization and electrical failure analysis
  • Perform electrical failure analysis to understand the root cause of the different yield issues and make recommendations for improvement to PE and Design.
  • Identify design marginalities and recommend design fix for circuit-related problems
  • Perform data analysis through analysis/statistic tools, summarize, present and publish data/result to all associated groups.
  • Design and run DOE to drive yield improvement activities.

C1+ Yield Engineering:

  • Lead Yield enhancement for C1+, including yield monitoring, performance to plan, drive C1+ yield program, coordinate FAB/PE/PYE effort to resolve process/device/test related yield issues.
  • Assess C1+ cum yield ROI, reference PTS flow/yield to influence C1+ test flow to minimize C1+ flow overkill and optimize C1+ coverage & quality. Work with PE on C1+ test/device optimization.
  • Bench characterization/EFA on C1+ failures, propose solution for baseline improvement.
  • High Stack yield enhancement. work with PYE/PE to monitor high stack yield performance to plan, resolve high stack yield challenge, coordinate FAB/PE/PYE effort to resolve process/device/test related yield issues.
  • Work and propose strategy to improve high stack yield such as additional C1/C1+ coverage or material channeling.


  • Bachelor's/Master's Degree in Electrical/Electronic Engineering, Microelectronic background is preferred.
  • Experience in yield analysis/EFA will be added advantage in consideration.
  • Good understanding of CMOS device physics is an added advantage
  • Excellent problem-solving and analytical skills.
  • Knowledge of CMOS circuit design and CAD/Simulation is an added advantage
  • Knowledge of NAND devices operations is an added advantage
  • Understanding of C1+ Probe Test flow and test methodology including array operation, customer feature and specification is an added advantage.
  • Willing to work flexible hours that overlap with different time zones, or nights and weekends if necessary.



Working Location : 1, North Coast Drive. 757432

We recruit, hire, train, promote, discipline and provide other conditions of employment without regard to a person's race, color, religion, sex, age, national origin, disability, sexual orientation, gender identity and expression, pregnancy, veteran’s status, or other classifications protected under law.  This includes providing reasonable accommodation for team members' disabilities or religious beliefs and practices.

Each manager, supervisor and team member is responsible for carrying out this policy. The EEO Administrator in Human Resources is responsible for administration of this policy. The administrator will monitor compliance and is available to answer any questions on EEO matters.

To request assistance with the application process, please contact Micron’s Human Resources Department at 1-800-336-8918 (or 208-368-4748).

Keywords:  Singapore || North West (SG-03) || Singapore (SG) || Frontend Manufacturing || College || Regular || Engineering || #LI-ST1 ||

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