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Principal NAND Innovation Engineer

San Jose, CA, US

 

Req. ID: 199203 

 

Micron Technology’s vision is to transform how the world uses information to enrich life. Our dedication to people, innovation, resourcefulness, collaboration, and customer focus allows us to fulfill our mission to be a global leader in memory and storage solutions. This means conducting business with integrity, accountability, and professionalism while supporting our global community.

 

NAND Pathfinding Team is chartered with envisioning, crafting, developing, and deploying innovative solutions to the most difficult problems faced by non-volatile memory systems today and in the future. Demonstrating a relatively small, very select group of technical contributors with expertise that ranges all the way from Si to system, the focus is on multi-functional solutions utilizing vertical integration. The team is a part of the Technology and Products Pathfinding Group led by only one of four Senior Fellows at Micron.

 

A successful candidate for NAND Innovation Engineer will have extensive experience in NAND Flash product development, either in technology development and/or product engineering. Significant depth of expertise in technology development (process integration, device development and array architecture and layout definitions) and/or product engineering (circuit behavior and debug, NAND Flash cell behavior, and array optimization) with a consistent track record of innovative solutions is required. In addition, functional skills demonstrating breadth of technical knowledge in Si devices, memory controller design and functionality, non-volatile system design and functionality is highly desirable. This is an outstanding role for a very creative and highly skilled NAND engineer!

 

Responsibilities include, but not limited to:

  • Innovate new solutions to complex multi-disciplinary problems by collaborating with other team members with skill sets ranging from Si to system.
  • Propose and evaluate new NAND array architecture, circuit placement, and operation concepts to overcome NAND scaling challenges for cost, performance, power, and reliability compared to today’s state of the art.
  • Lead cross-functional projects to pursue the proposed new NAND concepts.
  • Design and perform Si experiments and analysis on paper. Analyze data to quantify proposed NAND architecture and circuit changes utilizing critical analysis skills to determine the pros and cons, leading to a value proposition determination.
  • Exercise leadership skills by demonstrating the ability to drive complex projects from idea conception through evaluation and implementation.
  • Work closely with teams passionate about executing developed projects with high quality and minimized time to market.
  • Educate and mentor other technical contributors within the organization to raise their level of technical expertise.

 

A successful candidate for this position will have:

  • Technical expertise in technology development (process integration, device development and array architecture, and layout definitions) and/or product engineering (circuit behavior and debug, NAND Flash cell behavior and array optimization).
  • Consistent track record of innovative solutions taken from conception through implementation as demonstrated by patent portfolio and/or examples of competitive advantage gained over previous solutions.
  • Articulate vision for new concepts through excellent documentation and presentation skills.
  • Leadership skills to encourage, empower and drive peer contributors with varied skillsets towards a common goal.
  • Successful partnerships with internal and external domain specialists, advancing product development outcomes and setting the direction for future system products.

 

 

 

Minimum Qualifications:

  • Bachelor of Science (or higher) in Electrical Engineering (or a related field) and 5-15 years of circuit design and/or product engineering experience.
  • Knowledge of non-volatile memory process integration and array/circuit architectures.
  • Experience with process/device development and electrical failure analysis
  • Solid understanding of NAND layout principles and interconnect architectures.
  • Good understanding of NAND memory device physics for cell and CMOS circuits
  • Basic understanding of NAND memory design and systems.
  • Strong data analysis skills, including the ability to write basic scripts (Perl, Python, Matlab)
  • Strong leadership skills and multi-functional teamwork
  • Self-motivated and significant problem-solving skills

 

 

 

 

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.

 

For US Sites Only: To request assistance with the application process and/or for reasonable accommodations, please contact Micron’s Human Resources Department at 1-800-336-8918 or 208-368-4748 and/or by completing our General Contact Form


Keywords:  San Jose || California (US-CA) || United States (US) || Technology Development || Experienced || Regular || Engineering || #LI-GC1 || Tier 5 || 

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