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NAND Design Rule Engineer

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Date: Jan 26, 2019

Location: Boise, ID, US

Company: Micron

Req Id: 126177 



The Micron NAND Process R&D group is responsible for  developing state of the art high density NAND memory technologies. As an engineer within this organization you will be chartered with defining and maintaining physical design rules for current and future NAND technologies. 


Responsibilities include, but are not limited to:

  • Define full design rule (DR) documents to support technology development from conception to full production ramp.
  • Interact with design, product engineering, process & manufacturing to keep abreast of all technology developments to insure DR’s are accurate.
  • Support design rule checking (DRC) of both base and mask layers and interface with design teams on decisions concerning DRC waivers.
  • Define algorithms for generation of mask data from drawn base layer data.
  • Drive projects across multi-disciplinary teams focusing on layout and mask generation issues.
  • Drive diagnostic projects across multi-disciplinary teams to understand product and test structure failures and their interaction with layout and mask generated data.



  • Solid understanding of semiconductor device physics and silicon processing sub 0.1um.
  • Thorough knowledge of the scaling issues of flash memory (and ideally other semiconductor based non-volatile memory technologies) from both a device and product perspective.
  • Excellent understanding of design rules and the device physics and processing issues that control them.
  • Intimate comprehension of the interaction of base & mask layer and the ability to define the mask layer generation from the base layers.
  • Ability to handle multiple complex projects/issues at the same time and deliver results in a timely and orderly manner.
  • Project management skill to drive different teams to interact and solve complex problems in a timely manner



  • BS, MS or PhD in EE, Physics, Computer Science, Material Science or Chemistry.
  • At least 5 years in the semiconductor industry
We recruit, hire, train, promote, discipline and provide other conditions of employment without regard to a person's race, color, religion, sex, age, national origin, disability, sexual orientation, gender identity and expression, pregnancy, veteran’s status, or other classifications protected under law.  This includes providing reasonable accommodation for team members' disabilities or religious beliefs and practices.
Each manager, supervisor and team member is responsible for carrying out this policy. The EEO Administrator in Human Resources is responsible for administration of this policy. The administrator will monitor compliance and is available to answer any questions on EEO matters.
To request assistance with the application process, please contact Micron’s Human Resources Department at 1-800-336-8918 (or 208-368-4748).
Keywords: Boise || Idaho (US-ID) || United States (US) || Technology Development || Experienced || Regular || Engineering || #LI-SC2 ||

Nearest Major Market: Boise
Nearest Secondary Market: Meridian

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