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Design Engineer

Date: Dec 20, 2018

Location: Avezzano, AQ, IT

Company: Micron

Req. ID: 127110 

Recruiter: Rosario VINCIPROVA 

Job Description
As a Design Engineer in the Non-Volatile Engineering Group (NVE) at Micron Technology, Inc., you will be responsible for designing and analyzing digital and analog circuits used in the development of memory products. This includes designing, modeling parasitics, simulating, optimizing and floor planning circuits. In this position, you will work with and support the efforts of groups such as Product Engineering, Test, Probe, Quality and Reliability, Process Integration, Assembly and Marketing to proactively design products to optimize all manufacturing functions and assure the best cost, quality, reliability, time-to-market, and customer satisfaction. You will also be responsible for assisting in post-si design validation and defining and implementing design fixes.
Responsibilities and Tasks
Contribute to the Development of New Memory Products by Assisting With the Overall Design, Layout, and Optimization of Memory Circuits
  • Define the architecture and chip plan of the product, including placement and routing optimization
  • Interpret device Internal Architecture Specifications to produce required functionality
  • Design circuit blocks (analog schematics and digital RTL) to meet specifications
  • Develop and simulate embedded microcode
  • Model parasitics and create behavioral models
  • Synthesize and simulate digital blocks
  • Perform circuit simulations using standard industry simulators
  • Validate functionality and performance to meet specifications
  • Document and review final results with experts and stakeholders
  • Support automatic placement and routing of digital blocks
  • Work with Technology team to define array blocks and pitch cells
  • Define test mode specifications
  • Participate in new circuit conception and design as needed
  • Work with Process Integration to set model performance targets
  • Make sure that design operate within safe reliability operating range
  • Provide input to the layout team to ensure optimal layout for performance, die size, and reliability
Contribute to Cross-Group Communication to Work Towards Standardization and Group Success
  • Collaborate with Product Architect to define new features capabilities versus application requirements
  • Collaborate with the Product Engineering team to define test requirements and flows
  • Collaborate with CAD and R and D teams to define the process collateral, including standard cell library, process files, and verification runsets
  • Collaborate with CAD team to evaluate next generation software tools
  • Collaborate with Q and R and R and D teams to define Design for Reliability and Manufacturing improvements
  • Collaborate with the Package design team to ensure alignment between the design and package
  • Collaborate with the corporate ESD team to meet product ESD requirements
  • Collaborate with the Signal Integrity team to validate signal integrity and power delivery
Debug and Validate Products (Post-Silicon)
  • Provide training to product validation team on design architecture and features
  • Develop post-Si design validation plan and use it to validate internal functionality
  • Support Product Validation team in the debug of product, characterization and test issues
  • Implement design fixes and drive new tape-outs when required
Support Product Qualification and Production
  • Collaborate with Process R and D team to identify technology issues and to perform yield enhancement activities
  • Collaborate with the Qualification Team to meet all qualification milestones
  • Collaborate with Factory and Marketing on yield, quality and customer returns, and assist in developing screens, workarounds, and new tape-outs as required
Maintain Technical Expertise and Provide Training
  • Mentor and provide consultation to internal and external team members
  • Aid in communicating Best-Known Practices to entire department
  • Prepare detailed documentation as required
  • Contribute and participate in global Design forums
  • Participate in continuing education and competitor analysis
  • Participate in recruiting, and interviewing of new candidates
  • Assure protection of IP by means of Patent activity
Manage and Develop Projects and Team (Leads)
  • Plan and organize projects and resource requirements, including planning, scheduling activities and tasks, and management of design and layout resources
  • Serve as main point-of-contact for communication for design, layout, process and testing issues for projects
  • Track and monitor progress of project tasks
  • Prepare project status reports for upper management
Support Design Feasibility Studies During Product Feasibility Phase
  • Evaluate impact of requested features on effort, risk, and die size
  • Explore innovative solutions and improve product competitiveness
  • Work with R and D to define process technology capabilities versus application requirements
  • Support R and D to define and optimize design rules and technology placeholders for cost, performance and reliability

We recruit, hire, train, promote, discipline and provide other conditions of employment without regard to a person's race, color, religion, sex, age, national origin, disability, sexual orientation, gender identity and expression, pregnancy, veteran’s status, or other classifications protected under law.  This includes providing reasonable accommodation for team members' disabilities or religious beliefs and practices.


Each manager, supervisor and team member is responsible for carrying out this policy. The EEO Administrator in Human Resources is responsible for administration of this policy. The administrator will monitor compliance and is available to answer any questions on EEO matters.


To request assistance with the application process, please contact Micron’s Human Resources Department at 1-800-336-8918 (or 208-368-4748).


Keywords:  Avezzano || L'Aquila (IT-AQ) || Italy (IT) || NVE (Non-Volatile Engineering Group) || Experienced || Regular || Engineering || #LI-RV1 || 3DXP / NAND DE || 

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