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RD Package-Silicon Integration Senior Engineer

Date: Dec 4, 2017

Location: Taichung, TXQ, TW

Company: Micron

 

Req. ID: 102336 

As a Package Silicon Integration Engineer in Micron's Advanced Packaging Technology Development Group, you will be responsible for driving advanced IC package development for next generation silicon and package technologies. You will  collaborate with various functional teams such as silicon design, package design, wafer fab, package integration, test and QRA to formulate and execute the characterization and qualification plan. Demonstration of the technology is shown through meeting the requirements for thermal, mechanical, electrical, reliability and customer specifications.  You will drive the technology development through multiple phases of maturity and contribute to Micron's strategic objectives of Technology leadership.

 

Responsibilities include but are not limited to:

  • Develop and execute the plan to integrate new silicon technology with new package technologies for various memory applications according to Chip Package Interaction (CPI) business process.
  • Work with package design and development teams to complete technical risk assessment(TRA).
  • Work with scribe designers and assembly engineers to find solutions for dicing problems and implement relevant design rules and design FMEA.
  • Collaborate with R&D/manufacturing wafer fabs and packaging teams to solve relevant issues and improve yield, quality and manufacturability.
  • Contribute to development of new silicon and package technologies by engaging with Micron’s internal factories as well as OSATs.
  • Define test vehicles, plan DOEs, characterize enabling technologies, document best-known-process and hand-off to manufacturing.
  • Work with stakeholders to understand and roadmap package technology requirements for future silicon by customer and by market segment.
  • Identify technology, quality and business process gaps and develop and deploy needed solutions.
  • Be the contact window to the Si design, scribe design and wafer fab regarding the progress of key projects.

 

Qualifications:

• Minimum of 5 years’ experience in R&D/manufacturing wafer fab or IC Package development

• Strong interpersonal, oral and written English communications-skills

• Strong knowledge in Statistical Process Control & FMEA.

• Strong organizational skills

• Experience with Silicon integration and Design integration and mobile packaging is a plus.

• Chinese-language skills a plus

• Ability to work in Taiwan

 

Education:

• B.S. in - Mechanical, Electrical, Materials, Metallurgy, Physics or Chemistry, M.S preferred Or Equivalent work experience


We recruit, hire, train, promote, discipline and provide other conditions of employment without regard to a person's race, color, religion, sex, age, national origin, disability, sexual orientation, gender identity and expression, pregnancy, veteran’s status, or other classifications protected under law.  This includes providing reasonable accommodation for team members' disabilities or religious beliefs and practices.


Each manager, supervisor and team member is responsible for carrying out this policy. The EEO Administrator in Human Resources is responsible for administration of this policy. The administrator will monitor compliance and is available to answer any questions on EEO matters.


To request assistance with the application process, please contact Micron’s Human Resources Department at 1-800-336-8918 (or 208-368-4748).


Keywords:  Taichung || Taichung (TW-TXQ) || Taiwan (TW) || Technology Development || Experienced || Regular || Engineering || Not Applicable ||
 


Job Segment: Package Design, Thermal Engineering, Materials Science, Metallurgy, Manufacturing, Engineering, Science