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Design Verification Engineer

Date: Dec 5, 2017

Location: Milpitas, CA, US

Company: Micron


Req. ID: 102483 

As an ASIC Design Verification Engineer at Micron Technology, Inc., you will be responsible for design and verification on complex System on Chip (SoC) for flash based storage devices. In this position, the ASIC Design Verification Engineer performs constrained random simulation logging and debugging; analyzes chip architecture and microarchitecture; determines best implementation of DSP (Digital Signal Processing) algorithms and LDPC (low-density parity-check); reviews and refines ASIC (Application Specific Integrated Circuit) design flow including RTL (Register Transfer Level) coding an debug; designs and executes testing and regression methodology, including building constrained random driven verification and test-bench for block and system level verification and regression scripts automation; and runs both RTL and Gate level simulation.  Will also support silicon-bring up and debug.


Your responsibilities will include but are not limited to the following:


  • Block and system verification and validation on SSD controller
  • Develop software infrastructure and modeling for validation of SSD controller components
  • Code test benches in C/C++/Assembly Languages
  • Generate and debug tests on FPGA and sillicon
  • Good debug and bring-up skills on sillicon
  • Skillful in using Greenhills Debugger tools
  • Collaborate with different groups and good communication skills


Minimum Qualifications:


  • 5+ years of experience in storage market and knowledge of PCI Express, flash media
  • Master Degree in Electrical or Computer Engineering
  • Experience in SSD controller architecture
  • Experience in FPGA and sillicon bring up flow and debugging
  • Experience in developing test using C/C++/ARM instruction and validating ARM based SoC on FPGA and ASIC.
  • Experience in writing firmware like test programs to run on embedded processors for SSD controller engines.
  • Experience in developing automated flow using Python and Shell scripts.
  • Experience with gate level simulation involving SDF.
  • Experience with AMBA protocols and NAND Interfaces.
  • Must be willing to work evenings or weekends, if necessary.

We recruit, hire, train, promote, discipline and provide other conditions of employment without regard to a person's race, color, religion, sex, age, national origin, disability, sexual orientation, gender identity and expression, pregnancy, veteran’s status, or other classifications protected under law.  This includes providing reasonable accommodation for team members' disabilities or religious beliefs and practices.

Each manager, supervisor and team member is responsible for carrying out this policy. The EEO Administrator in Human Resources is responsible for administration of this policy. The administrator will monitor compliance and is available to answer any questions on EEO matters.

To request assistance with the application process, please contact Micron’s Human Resources Department at 1-800-336-8918 (or 208-368-4748).

Keywords:  Milpitas || California (US-CA) || United States (US) || ACG (Advanced Controller Group) || Experienced || Regular || Engineering || Not Applicable ||

Nearest Major Market: San Jose
Nearest Secondary Market: Palo Alto

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