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R&D DRAM CMOS Process Integration Manager

Date: Apr 12, 2018

Location: Higashi Hiroshima, 34, JP

Company: Micron


Req. ID: 104043 

Micron's Technology Development (TD) team is looking for a candidate to fill the position of CMOS Process Integration Manager to oversee CMOS development for all DRAM technology nodes. Ideal candidate will have exceptional record of accomplishments in leading a strong technology team. This position will be based in Hiroshima, Japan or Boise, US and travel between these sites on a periodic basis will be a core requirement.


Job Description:

  • As a CMOS Integration Manager in DRAM, you will manage a team of Process Integration (PI) engineers in Boise (F4) and Hiroshima (F15) TD sites.
  • You will be responsible for coordinating PI activities to enable CMOS development for all technology nodes – through careful design of experiments to improve device performance to meet product needs.
  • You will be responsible for timely development of CMOS to intercept various technology node milestones and adapt to changes in process during yield improvement and transfer to MFG.
  • You will be responsible for the creation and validation of relevant design rules to enable competitive DRAM products.
  • Strong engagement & collaboration with process module development teams in both Boise and Hiroshima is required.
  • Strong engagement & collaboration with design and product engineering teams is required.
  • Strong engagement with various device technology teams responsible for compact model generation, reliability analysis and model generation, design rule creation, and electrical validations is required
  • You will be responsible for providing regular summary and detailed updates to executive leadership.


Successful candidate requirements are:

  • More than 10 years experience managing teams in a R&D environment with proven leadership skills
  • Deep understanding of CMOS devices, process integration and the state-of-art DRAM technology
  • Knowledge of experimental design, data analysis, SPC, design rules
  • Excellent project management skills
  • Excellent communication & presentation skills, both oral and written – in English


    Preferred candidates will have: 

  • Experience in working in a global environment, particularly between Japan & US
  • Fluency in Japanese


Education:  MS/PhD in Electrical/Electronics Engineering with relevant industry experience in areas outlined above. 

We recruit, hire, train, promote, discipline and provide other conditions of employment without regard to a person's race, color, religion, sex, age, national origin, disability, sexual orientation, gender identity and expression, pregnancy, veteran’s status, or other classifications protected under law.  This includes providing reasonable accommodation for team members' disabilities or religious beliefs and practices.

Each manager, supervisor and team member is responsible for carrying out this policy. The EEO Administrator in Human Resources is responsible for administration of this policy. The administrator will monitor compliance and is available to answer any questions on EEO matters.

To request assistance with the application process, please contact Micron’s Human Resources Department at 1-800-336-8918 (or 208-368-4748).

Keywords:  Higashi Hiroshima || Hiroshima (JP-34) || Japan (JP) || Technology Development || Experienced || Regular || Engineering || #LI-MW1 ||

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